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High-Power, Reliable DFB Lasers for AI & Data Optical Interconnects

AI and hyperscale data centers require light sources that combine high power, spectral stability, and scalability. Sivers Photonics’ continuous-wave (CW) DFB lasers deliver the optical performance and cost-efficiency needed for next-generation AI, machine learning, and data communication architectures—enabling both scale-up and scale-out networks.

These chips are designed for system developers, module integrators, and OEMs designing optical interconnects, co-packaged optics (CPO), optical I/O, and high-speed data links for AI accelerators, data centers, and high-performance computing (HPC) clusters.

Why Sivers for Data Communications, AI and ML?

High-yield ridge-waveguide and dual-ridge architectures ensure consistent wavelength control and performance.

Ultra-low FIT rates (<1) provide the reliability required for hyperscale data centers
and AI/ML workloads.

Etched-facet, on-wafer coated design allows full optical testing before dicing — reducing cost and improving reliability.

Compact chip design enables easy integration into miniaturized optical modules.

On-wafer coating and testing eliminate bar processing, improving yield and scalability.

What Problems We Solve

Our 70 mW and 100 mW DFBs are perfectly suited to 800G and 1.6T pluggable transceivers, with wafer-level processing and testing that make them among the most cost-effective options available on the market. Our DFB laser arrays directly address the performance and integration challenges driving Co-Packaged Optics and Optical I/O development – while delivering high optical power and precise wavelength control, the array format simplifies assembly by minimizing alignment steps ultimately making packaging quicker and most cost effective.

Key Benefits

  • Output powers up to 100 mW across O-band
  • Proven ridge-waveguide architecture delivers high yield, low cost, and stable performance
  • Etched-facet, on-wafer coating and testing eliminate bar processing reducing cost and improving yield
  • Dual ridge approach increases chip yield
  • Array format simplifies assembly and packaging, lowering total manufacturing cost
  • 200/400 GHz channel spacing options